`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/02 09:55:24
// Design Name: 
// Module Name: decoder_38
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module decoder_38(
    input [2:0] data,
    input [2:0] en,
    output reg [7:0] led
    );

    wire en_out, en_not[1:0];

    not U_not_0(en_not[0], en[0]);
    not U_not_1(en_not[1], en[1]);
    and U_and_0(en_out, en_not[0], en_not[1], en[2]);

    always @ (*) begin
        case (data)
            3'b000: led = en_out ? 8'b0000_0001 : 8'b0000_0000;
            3'b001: led = en_out ? 8'b0000_0010 : 8'b0000_0000;
            3'b010: led = en_out ? 8'b0000_0100 : 8'b0000_0000;
            3'b011: led = en_out ? 8'b0000_1000 : 8'b0000_0000;
            3'b100: led = en_out ? 8'b0001_0000 : 8'b0000_0000;
            3'b101: led = en_out ? 8'b0010_0000 : 8'b0000_0000;
            3'b110: led = en_out ? 8'b0100_0000 : 8'b0000_0000;
            3'b111: led = en_out ? 8'b1000_0000 : 8'b0000_0000;
            default: led = 8'b0000_0000;
        endcase
    end
endmodule
